Tushar Krishna


Associate Professor

Contact

  • Office: Klaus Advanced Computing Center, Room 2318
  • Mailing Address: 266 Ferst Drive, Atlanta, GA 30332
  • Email: tushar <at> ece <dot> gatech <dot> edu

Education

  • PhD in Electrical Engineering and Computer Science, MIT, 2014
  • MSE in Electrical Engineering, Princeton University, 2009
  • B.Tech in Electrical Engineering, IIT Delhi, 2007

Brief Bio

Tushar Krishna is an Associate Professor in the School of Electrical and Computer Engineering (ECE) at Georgia Institute of Technology, with a courtesy appointment in Computer Science. He held the ON Semiconductor (Endowed) Junior Professorship in ECE at Georgia Tech from 2019-2021. He has also been a visiting professor at MIT EECS + CSAIL, Harvard University CS and a researcher at Intel’s VSSAD group. He has a Ph.D. in Electrical Engineering and Computer Science from MIT (2014), a M.S.E in Electrical Engineering from Princeton University (2009), and a B.Tech in Electrical Engineering from the Indian Institute of Technology (IIT) Delhi (2007).

Dr. Krishna’s research spans computer architecture, interconnection networks, networks-on-chip (NoC), and AI/ML accelerator systems – with a focus on optimizing data movement in modern computing platforms. His research is funded via multiple awards from NSF, DARPA, IARPA, SRC (including JUMP2.0), Department of Energy, Intel, Google, Meta/Facebook, Qualcomm and TSMC. His papers have been cited over 21,000 times. He has been a recipient of multiple IEEE Micro’s Top Picks and best paper awards across computer architecture and design-automation conferences.  He is part of the Halls of Fame of all three of the premier computer architecture conferences: MICRO, HPCA and ISCA. He was a recipient of the “Under 40 Innovators Award” at DAC in 2025.

Dr. Krishna currently serves as an Associate Director for the Center for Research into Novel Computing Hierarchies (CRNCH) – a cross-disciplinary research center at Georgia Tech. He is also a co-chair of the Chakra Execution Traces and Benchmarks Working group within ML Commons.

Research Interests

  • Computer System Architecture
  • Interconnection Networks and On-Chip Networks
  • AI/ML Inference Accelerators
  • AI/ML Distributed Training Platforms
  • ML-assisted System Design
  • Reconfigurable Computing
  • Edge Computing

 Quick Links


Teaching


Professional Service

  • Conference Organization 
  • Technical Program Committee
    • MICRO 2025
    • ASPLOS 2025
    • IEEE Micro Top Picks 2025
    • ISCA 2025
    • MLSys 2025
    • Rising Stars in MLSystems 2025
    • MICRO 2024
    • ISCA 2024
    • MLSys 2024
    • MICRO 2023
    • IEEE Micro Top Picks 2023
    • MLSys 2023
    • ASPLOS 2023
    • DATE 2023
      • TPC topic co-chair for “Design Methodologies for Machine Learning Architectures”
    • MICRO 2022
    • SC 2022
    • MLSys 2022
    • IEEE Micro Top Picks 2022
    • HPCA 2022
    • DATE 2022
      • TPC topic co-chair for “Design Methodologies for Machine Learning Architectures”
    • MICRO 2021
    • ISCA 2021
    • ISCAS 2021
    • DATE 2021
      • TPC topic co-chair for “Design Methodologies for Machine Learning Architectures”
    • HPCA 2021
    • MICRO 2020
    • ISCA 2020
    • IEEE Micro Top Picks 2020
    • DATE 2020
    • Hot Interconnects 2019
    • MICRO 2019
    • PACT 2019
    • ISCA 2019
    • DAC 2019
      • TPC track chair for “In-Package and On-Chip Communication and Networks-on-Chip”
    • DATE 2019
    • AISTECS 2019
    • MICRO 2018
    • DAC 2018
    • IPDPS 2018
    • ISPASS 2018
    • DATE 2018
    • DAC 2017
    • DATE 2017
    • MICRO 2016
    • Hot Interconnects 2016
    • DAC 2016
  • Extended Review Committee (ERC)
    • HPCA 2025
    • HPCA 2023
    • ASPLOS 2019
    • HPCA 2019
    • MICRO 2017
    • ISCA 2017
    • PACT 2016


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