Tushar Krishna

Associate Professor

• School of Electrical and Computer Engineering  
• School of Computer Science  (Adjunct)  
• Georgia Institute of Technology  

Contact

• Office: Klaus Advanced Computing Center, Room 2318
• Mailing Address: 266 Ferst Drive, Atlanta, GA 30332
• Email: tushar <at> ece <dot> gatech <dot> edu

Education

• PhD in Electrical Engineering and Computer Science, MIT, 2014
• MSE in Electrical Engineering, Princeton University, 2009
• B.Tech in Electrical Engineering, IIT Delhi, 2007

Brief Bio

Tushar Krishna is an Associate Professor in the School of Electrical and Computer Engineering at Georgia Tech. He held the ON Semiconductor (Endowed) Junior Professorship from 2019-2021. He has a Ph.D. in Electrical Engineering and Computer Science from MIT (2014), a M.S.E in Electrical Engineering from Princeton University (2009), and a B.Tech in Electrical Engineering from the Indian Institute of Technology (IIT) Delhi (2007). Before joining Georgia Tech in 2015, Dr. Krishna spent a year as a researcher at the VSSAD group at Intel, Massachusetts.

Dr. Krishna’s research spans computer architecture, interconnection networks, networks-on-chip (NoC), and deep learning accelerators – with a focus on optimizing data movement in modern computing systems. His research is funded via multiple awards from NSF, DARPA, IARPA, Department of Energy, Intel, Google, Facebook, Qualcomm and TSMC. His papers have been cited over 10,000 times. Three of his papers have been selected for IEEE Micro’s Top Picks from Computer Architecture, one more received an honorable mention, and two have won best paper awards. He received the “Class of 1940 Course Survey Teaching Effectiveness” Award from Georgia Tech in 2018 and the “Roger P. Webb Outstanding Junior Faculty Award” from the School of ECE in Georgia Tech in 2021.

Research Interests

• Computer System Architecture
• Interconnection Networks and On-Chip Networks
• Reconfigurable Computing
• Deep Learning Accelerators
• ML-assisted System Design
• Edge/Fog Computing

 Quick Links

• Synergy Lab
• Latest News
• Publications
• Released Tools
  • NoC: Garnet2.0, OpenSMART
  • DNN Accelerator Design-Space Exploration: MAESTRO,  SCALE-sim, STONNE
  • DNN Accelerator RTL: MAERI
  • Distributed DNN Training: ASTRA-sim

Teaching

• Spring 2022: Interconnection Networks for High-Performance Systems
• Fall 2021: Architecture, Systems, Concurrency, and Energy in Computation
• Spring 2021: Interconnection Networks for High-Performance Systems
• Spring 2021: Architecture, Systems, Concurrency, and Energy in Computation
• Spring 2020: Interconnection Networks for High-Performance Systems
• Spring 2020: Architecture, Systems, Concurrency, and Energy in Computation
• Fall 2019: Advanced Computer Architecture
• Spring 2019: Hardware Acceleration for Machine Learning
• Spring 2019: Interconnection Networks for High-Performance Systems
• Fall 2018: Architecture, Concurrency, and Energy in Computation
• Spring 2018: Architecture, Concurrency, and Energy in Computation
• Spring 2018: Interconnection Networks for High-Performance Systems
• Summer 2017: Networks-on-Chip @ ACACES Summer School
• Spring 2017: Interconnection Networks
• Fall 2016: Advanced Computer Architecture
• Spring 2016: Interconnection Networks
• Fall 2015: Advanced Computer Architecture

Professional Service

• Conference Organization 
  • Artifacts Evaluation Co-Chair: HPCA 2022
  • General Chair: NOCS 2021
  • Tutorials and Workshops Chair: ISPASS 2021
  • TPC Co-Chair: NOCS 2020
  • Co-Chair: RISC-A 2019
  • Special Sessions Co-Chair: NOCS 2019
  • Co-Chair: Inaugural RISC-A 2018
  • Publicity Co-Chair: NOCS 2018
  • Student Travel Grants Co-Chair: PACT 2018
  • Student Travel Grants Co-Chair: ISCA 2017
  • Tutorials and Workshops Chair: ASPLOS 2016
• Technical Program Committee
  • SC 2022
  • MLSys 2022
  • IEEE Micro Top Picks 2022
  • HPCA 2022
  • DATE 2022
    • TPC track co-chair for “Design Methodologies for Machine Learning Architectures”
  • MICRO 2021
  • ISCA 2021
  • ISCAS 2021
  • DATE 2021
    • TPC track co-chair for “Design Methodologies for Machine Learning Architectures”
  • HPCA 2021
  • MICRO 2020
  • ISCA 2020
  • IEEE Micro Top Picks 2020
  • DATE 2020
  • Hot Interconnects 2019
  • MICRO 2019
  • PACT 2019
  • ISCA 2019
  • DAC 2019
    • TPC track chair for “In-Package and On-Chip Communication and Networks-on-Chip”
  • DATE 2019
  • AISTECS 2019
  • MICRO 2018
  • DAC 2018
  • IPDPS 2018
  • ISPASS 2018
  • DATE 2018
  • DAC 2017
  • DATE 2017
  • MICRO 2016
  • Hot Interconnects 2016
  • DAC 2016
• Extended Review Committee (ERC)
  • ASPLOS 2019
  • HPCA 2019
  • MICRO 2017
  • ISCA 2017
  • PACT 2016