ECE 6115 A / CS 8803 – ICN
|Instructor||Professor Tushar Krishna|
|Office Hours||By Appointment|
|Hours||Tu & Th 9:30 – 10:45 am|
|Room||VL C341 + Bluejeans. FIRST CLASS (Jan 11) CANCELLED. Video will be uploaded here.|
Prerequisite(s): ECE 4100 / ECE 6100 (Advanced Computer Architecture) or CS 4290 / CS 6290 (High Performance Computer Architecture). Simultaneous registration will be allowed.
Interconnection Networks form the backbone of all computer systems today. They occur at various scales across all high-performance systems – systolic-arrays within Google’s Deep Learning TPU, high-bandwidth crossbars inside modern GPUs, soft transport macros on FPGAs, mesh networks-on-chip (NoC) in many-core processors, interposer fabrics on package, QPI in multi-socket servers, Infiniband in supercomputers/clusters, and Fat-Tree datacenter networks in the cloud. The growing emphasis on parallelism, scalability, and energy-efficiency across all these systems makes the design of the communication fabric critical to both high-performance and low power consumption.
This course will examine the similarities, differences and trade-offs in the architecture and implementation of interconnection fabrics across all these systems. Given the breadth of topic areas (computer architecture, VLSI interconnects, computer networks, and distributed systems), students will get a glimpse into designing systems and optimizing for data movement at various scales – from on-chip to cloud-scale.
This year, there will be a particular focus on the role of interconnection networks in Deep Learning Accelerators and Systems during Inference (e.g., Google TPU, NVIDIA DLA, MIT Eyeriss) and Distributed Training (e.g., Google Cloud TPU, Facebook Zion, NVIDIA DGX-2)
This is an advanced graduate course, structured around a mix of lectures, student presentations, paper critiques, lab assignments and a final project.
In the first half of the course, lectures will cover the fundamentals of interconnection networks: topology, routing, flow-control, microarchitecture, network and system interfaces. In addition, a series of programming-heavy labs will bring everyone up to speed with an interconnection networks simulator Garnet, that is distributed within the gem5 (www.gem5.org) open source full-system multi-core simulator.
In the second half of the course, students will present and critique research papers on interconnection networks from a breadth of computing domains (computer architecture, circuits, HPC, datacenters, DNN Accelerators). Students will also work on a research project focused on addressing a research challenge in interconnection networks. Projects aligned with students’ own graduate research (MS/PhD) will be encouraged if they have an exciting networks component. Projects from past iterations of the course have led to publications in top-tier conferences such as HPCA, ASPLOS, MICRO, ICCAD, ISPASS and NOCS.
Minor in ECE for CS Students: To get credits for a minor in ECE, register for the ECE section.
Course Syllabus: CourseOutline_ICN.pdf
Course Schedule and Readings:
|Paper Critiques||10% [Best of 10]|
|Project – Proposal||5%|
|Project – Milestones||10%|
|Project – Presentation||10%|
|Project – Final Report||10%|
- Module 1: Introduction [Slides][Video]
- Module 2: Topology
- Module 3: Routing
- Module 4: Deadlocks
- Module 5: Flow-Control
- Module 6: Router Microarchitecture
- Module 7: System Interactions
- Setup for Garnet for Labs
- Within Georgia Tech: How to setup gem5/garnet at Georgia Tech.
- External copy of same repo: https://bitbucket.org/synergy-lab/gem5_gt/
- Lab1: Running Garnet
- Lab2: Topology
- Lab3: Deadlock
Textbook(s) and Readings
N. E. Jerger, T. Krishna and L.-S Peh, “On-Chip Networks, 2nd Edition”, Morgan Claypool Publishers, 2017. [optional]
W. J. Dally and B. Towles, “Principles and Practices of Interconnection Networks,” Morgan Kauffman Publishers, 2004. [optional]
J. Duato, S. Yalamanchili, L. Ni, “Interconnection Networks: An Engineering Approach,” Morgan Kauffman Publishers, 2002. [optional]
There will be a lot of additional readings of recent research papers from conferences such as ISCA, MICRO, HPCA, ASPLOS, SIGCOMM, NSDI, NOCS, DATE, DAC, ISSCC
I am an undergrad. Would this course be useful for me?
If you are interested in applying to graduate school, and/or work in industry in the field of computer systems, expertise in this area will be a unique skill set to have. You will also get to work on open research problems in a relatively nascent field, in a structured setting (simulator, workloads etc that I will provide) without shooting in the dark.
I am a MS/PhD student and am (interested in) working in the area of Computer Architecture/Interconnection Networks/Networks-on-Chip. Can I take this course and use the course project towards my Masters/PhD thesis.
Yes. I am open to aligning the course project with your actual thesis work as long as there is an interesting networks component.
What is the required background? If I am an ECE student, do I need a CS (parallel programming/compilers/OS) background or if I am a CS student, do I need an ECE (circuits, RTL) background?
The required background is an understanding of computer architecture (ECE 4100 / ECE 6100 / CS 4290 / CS 6290) and familiarity with basic C++ programming. We will be using a simulator called gem5 which is written in C++. However, as with any research in computer architecture, you can choose to work on the circuits end of the computing stack, the microarchitecture end, or the software end. Interconnection Networks are no different. A diverse set of backgrounds is good, and in fact encouraged, as we read and discuss papers in the class. For the project, if someone wanted to implement a new NoC in Verilog instead of C++ and synthesize it to study power consumption, or wanted to hack LLVM to inject hints in the code that the NoC could use for power management, I would encourage both directions.
Is there a lot of programming in the course?
The labs in Garnet will involve C++ programming. The labs themselves will not be as programming heavy as say a CS systems course, but will involve implementing network optimizations within the framework of Garnet. The research project could involve C++ and/or RTL programming depending on the topic you choose.
What sort of research projects are part of the course?
We will run a suite of projects involving interconnection networks for many-core processors and datacenter networks involving novel topologies and routing algorithms. In addition, this year a suite of projects will focus on the interconnects inside Deep Learning Accelerators. We have a framework to model different DNN dataflows and you will have the opportunity to design the full accelerator RTL that can be mapped on a FPGA. We plan to have projects involving implementing and comparing a Google TPU, NVIDIA DLA, and MIT Eyeriss — all specialized DNN accelerators. We will also have a suite of projects focused on using an interconnection of Raspberry Pis as a IoT platform and running various IoT applications on them.
Is there scope for publications?
Yes, ample scope. Most of the projects will be on designing novel networks for emerging architectures. If the results from your course project look promising, we can write a paper on it over summer and I will fund your travel to go present it. Past projects from the course have led to publications to HPCA, ASPLOS, ICCAD, ISPASS and NOCS.
Students are expected to abide by the Georgia Tech Academic Honor Code. Honest and ethical behavior is expected at all times. All incidents of suspected dishonesty will be reported to and handled by the office of student affairs. You will have to do all assignments individually unless explicitly told otherwise. You may discuss with classmates but you may not copy any solution (or any part of a solution).