Advanced Computer Architecture (Fall 2015)

ECE6100/ECE4100/CS4290/CS6290 B

Fall 2015

Course Overview

This course is a study of the evolution of computer architecture and the factors influencing the design of hardware and software elements of computer systems. Topics may include: instruction set design; processor micro-architecture and pipelining; cache and virtual memory organizations; protection and sharing; I/O and interrupts; in-order and out-of-order superscalar architectures; VLIW machines; vector supercomputers; multithreaded architectures; symmetric multiprocessors; memory models and synchronization; embedded systems; and parallel computers.

Course Information

Lectures
Hours	Tue & Thu 3:05 – 4:25 pm
Room	Van Leer W200

Recitations
Hours	Mon & Fri 6 – 7 pm
Room	KACB 3100 (Mon), KACB 2447 (Fri)

Piazza

We will be using Piazza for class discussion. The system is highly catered to getting you help fast and efficiently from classmates, the TAs, and myself. Rather than emailing questions to the teaching staff, I encourage you to post your questions on Piazza.

Find our class page at: https://piazza.com/gatech/fall2015/ece6100b/

Course Staff

Instructor	Professor Tushar Krishna
Email	tushar.krishna@ece.gatech.edu
Office	KACB 2318
Office Hours	Tue & Thu 4:30 – 5 pm [Van Leer W200 after class]
Office Hours	Wed 3 – 4 pm [KACB 2318]

Teaching Assistants	Shravan Ramani	Tushar Supe
Email	sramani9@gatech.edu	tusharsupe@gatech.edu
Office Hours	Wed 12:30 – 1:30 pm	Thu 10:30 – 11:30 pm
Office Hours	[Next to KACB 2332]	[Next to KACB 2332]

Course Material

There is no required textbook for this course, but we recommend Computer Architecture: A Quantitative Approach by John Hennessy and David Patterson, 5th Edition, Morgan Kauffman, 2012.

Selected readings from the book will be listed for each lecture in the course schedule.

Grading

Lab 1	5%
Lab 2	10%
Lab 3	10%
Lab 4	10%
HW 1	2%
HW 2	2%
Participation	1%
Midterm 1	20%
Midterm 2	20%
Final	20%

Schedule

Week	Date	Lecture	Background Readings	Due Dates
1	Aug 18 (Tu)	L01: Introduction
1	Aug 21 (Th)	L02: History	H&P Ch1: p2-61, IBM 360	Lab 1 (Aug 21 Fri @1pm)
2	Aug 25 (Tu)	L03: Single Cycle MIPS Implementation	H&P App A: p2-32
2	Aug 27 (Th)	L04: Simple Pipeline & Hazards	H&P App C: p2-25
3	Sep 1 (Tu)	L05: Branch Prediction	H&P App C: p26-29, Ch3: p162-167, 203-208 S. Mcfarling, “Combining Branch Predictors,” WRL Technical Note TN-36 1993. Kessler, “The Alpha 21264 Microprocessor,” IEEE Micro 1999. E. Sprangle et al, “The Agree Predictor: A Mechanism for Reducing Negative Branch History Interference“, ISCA 1997. D. Jimenez and C. Lin, “Dynamic Branch Prediction with Perceptrons,” HPCA 2001. A. Seznec and P. Michaud. “A case for (partially)-tagged geometric history length predictors“. Journal of Instruction Level Parallelism 2006.
3	Sep 3 (Th)	L06: Branch Prediction + Superscalar Pipelines	Patel et al., “Critical Issues Regarding the Trace Cache Fetch Mechanism,” UMich TR 1997.
4	Sep 8 (Tu)	L07: OoO Execution I : Hazards and Register Renaming	H&P Ch 3: 167-170
4	Sep 10 (Th)	L08: OoO Execution II: Tomasulo’s Algorithm	H&P Ch3: 170-183
5	Sep 15 (Tu)	L09: OoO Execution III: Reorder Buffer	H&P Ch3: 183-192, 197-201
5	Sep 17 (Th)	L10: Speculative Execution		Lab 2 (Sep 18 Fri @ 11:55pm)
6	Sep 22 (Tu)	L11: Midterm I Review		HW1 (Sep 21 Mon @ 11:55pm)
6	Sep 24 (Th)	Midterm I
7	Sep 29 (Tu)	L12: Caches I	H&P App B: p2-40, Ch2: 72-96 M. Qureshi & Y. N. Patt, “Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches,” MICRO 2006 D. Sanchez & C. Kozyrakis, “The ZCache: Decoupling Ways and Associativity,” MICRO 2010
7	Oct 1 (Th)	L13: Caches II
8	Oct 6 (Tu)	L14: Caches III
8	Oct 8 (Th)	L15: Virtual Memory I	Ch 2: p105-131; App B: p40-60
9	Oct 13 (Tu)	Fall Break		Lab 3 Part A (Oct 14 Wed @ 11:55 pm)
9	Oct 15 (Th)	L16: Virtual Memory II	Ch 2: p105-131; App B: p40-60
10	Oct 20 (Tu)	L17: Multiprocessors	Ch5: p344-351, 400-405, App I
10	Oct 22 (Th)	L18: Networks-on-Chip I	H& P App F Topology J. Kim, D. Abts, & W. J. Dally, “Flattened Butterfly: A Cost-Efficient Topology for High-Radix Networks,” ISCA 2007 Routing D. Seo, A. Ali, W-T Lim, N. Rafique, M. Thottethodi, “Near-Optimal Worst-case Throughput Routing for Two-Dimensional Mesh Networks”, ISCA 2005. Flow Control/Router Microarchitecture T. Moscriboda & O. Mutlu, “A Case for Bufferless Routing in On-Chip Networks,” ISCA 2009 A. Kumar, L-S. Peh, P. Kundu, & N. K. Jha, “Towards Ideal On-Chip Communication Using Express Virtual Channels,” IEEE Micro Top Picks of Architecture Conferences 2008. T. Krishna, C-H Chen, W-C. Kwon, L-S Peh, “Breaking the On-Chip Latency Barrier Using SMART,” HPCA 2013 NoC Prototypes from Industry J. Howard et al., “A 48-Core IA-32 Message-Passing Processor with DVFS in 45nm CMOS,” ISSCC 2010 [Intel] D. Wentlaff et al, “On-Chip Interconnection Architecture of the Tile Processor,” IEEE Micro 2007 [Tilera]	Lab 3 Part B+C (Oct 23 Fri @ 11:55 pm)
11	Oct 27 (Tu)	L19: Networks-on-Chip II
11	Oct 29 (Th)	L20: Networks-on-Chip III
12	Nov 3 (Tu)	Midterm II
12	Nov 5 (Th)	L21: Networks-on-Chip IV
13	Nov 10 (Tu)	L22: Cache Coherence I	Coherence: H&P Ch5: p351-386 N. Agarwal, L-S. Peh, and N. K. Jha, “In-Network Snoop Ordering: Snoopy Coherence on Unordered Interconnects,” HPCA 2009 D. Vantrease, M. H. Lipasti, and N. Binkert, “Atomic Coherence: Leveraging Nanophotonics to Build Race-Free Cache Coherence Protocols,” HPCA 2011 Cache Management (Private vs Shared) C. Kim, D. Burger, and S. W. Keckler, “An Adaptive, Non-Uniform Cache Structure for Wire-Delay dominated On-Chip Caches,” ASPLOS 2002 J. Chang and G. S. Sohi, “Cooperative Caching for Chip Multiprocessors,” ISCA 2006 N. Hardavellas, M. Ferdman, B. Falsafi, and A, Ailamaki, “Reactive NUCA: Near-Optimal Block Placement and Replication in Distributed Caches”, ISCA 2009 G. Kurian, S. Devadas, and O. Khan, “Locality-Aware Data Replication in the Last-Level Cache,” HPCA 2014 B. M. Beckmann and David A. Wood, “Transmission Line Caches,” MICRO 2003 W-C Kwon, T. Krishna and L-S. Peh, “Locality-Oblivious Cache Organization leveraging Single-Cycle Multi-Hop NoCs,” ASPLOS 2014 Consistency: H&P Ch5: p392-400
13	Nov 12 (Th)	L23: Cache Coherence II
14	Nov 17 (Tu)	L24: Cache Coherence III
14	Nov 19 (Th)	L25: Cache Coherence IV + Memory Consistency		Lab 4 Part A+B(+C) (Nov 20, Fri @ 11:55 pm)
15	Nov 24 (Tu)	L26: Multithreading		Lab 4 Part D+E (Nov 24, Wed @ 11:55 pm)
15	Nov 26 (Th)	Thanksgiving Break
16	Dec 1 (Tu)	L27: Vector Computers
16	Dec 3 (Th)	L28: Future Trends + Review

Honor Code:

Students are expected to abide by the Georgia Tech Academic Honor Code. Honest and ethical behavior is expected at all times. All incidents of suspected dishonesty will be reported to and handled by the office of student affairs. You will have to do all assignments individually unless explicitly told otherwise. You may discuss with classmates but you may not copy any solution (or any part of a solution).