Teaching Networks-on-Chip (ACACES 2017)

Networks-on-Chip (ACACES 2017)

High-Performance On-Chip Interconnects for Emerging SoCs
ACACES 2017


Course Information

 Instructor   Professor Tushar Krishna
 Email   tushar@ece.gatech.edu
 Website  http://tusharkrishna.ece.gatech.edu

Prerequisite(s):  Advanced Computer Architecture or Equivalent


Course Description

Interconnection Networks refer to the communication fabric interconnecting various components of a computer system. They occur at various scales – from on-chip networks (OCN)/Networks-on-Chip (NoCs) in billion-transistor many-core chips, to custom high-speed wired networks in HPC supercomputers, to optical fiber networks within datacenters. The growing emphasis on parallelism, distributed computing, heterogeneity, and energy-efficiency across all these systems makes the design of the communication fabric critical to both high-performance and low power consumption.
This course examines the architecture, design methodology, and trade-offs of interconnection networks. The material covered in this course bridges the gap between disciplines/courses such as VLSI interconnects, digital communication, computer architecture, distributed systems, and computer networks. The focus of the course will be on on-chip interconnection networks for emerging SoCs that comprise heterogeneous cores and accelerators. The insights and learning will span chip-scale, rack-scale, and datacenter-scale networks as well.

Lectures will cover the fundamental building blocks of interconnection networks, getting to the research frontier at each level – topology, routing, flow-control, microarchitecture, network interfaces, and system interactions. By the end of the course, students will acquire the intuition and skill-set required to build and evaluate a state-of-the-art network-on-chip that meets desired performance, area, and energy specs for the target system (homogeneous many-core, heterogeneous SoC, or a spatial accelerator).


Textbook(s) [optional]

N. E. Jerger, T. Krishna and L.-S Peh, “On-Chip Networks, Second Edition” Morgan Claypool Publishers, 2017.

W. J. Dally and B. Towles, “Principles and Practices of Interconnection Networks,” Morgan Kauffman Publishers, 2004.

J. Duato, S. Yalamanchili, L. Ni, “Interconnection Networks: An Engineering Approach,” Morgan Kauffman Publishers, 2002.


Schedule

 Date  Topic   Slides    Additional Readings  
 Jul 10  Intro+Topology   L01-Intro+Topology   [MICRO2007] FBFLY
 Jul 11  Routing   L02-Routing  [PACT2011] ARIADNE
 Jul 13  Flow Control   L03-FlowControl  [HPCA2013] SMART
 Jul 14  Microarch + Case Studies  Intel Skylake Mesh