Teaching Interconnection Networks (Spring 2016)

Interconnection Networks (Spring 2016)

ECE 8823 A / CS 8803 – ICN

Spring 2016


Course Information

 Instructor   Professor Tushar Krishna
Email   tushar@ece.gatech.edu
Office   KACB 2318
 Office Hours   Mon and Wed after class
Tue 3-4 pm

 

  Lectures
  Hours     Mon & Wed 3:05 – 4:25 pm
  Room     Klaus 1447

(First Lecture: January 11, 2016)

Prerequisite(s):   ECE 4100 / ECE 6100 (Advanced Computer Architecture) or  CS 4290 / CS 6290 (High Performance Computer Architecture)

 


Course Description

Interconnection Networks refer to the communication fabric interconnecting various components of a computer system. They occur at various scales – from on-chip networks (OCN)/Networks-on-Chip (NoCs) in billion-transistor many-core chips, to custom high-speed wired networks in HPC supercomputers, to optical fiber networks within datacenters. The growing emphasis on parallelism, distributed computing, and energy-efficiency across all these systems makes the design of the communication fabric critical to both high-performance and low power consumption. This course examines the architecture, design methodology, and trade-offs of interconnection networks. The material covered in this course bridges the gap between disciplines/courses such as VLSI interconnects, digital communication, computer architecture, distributed systems, and computer networks. The overall focus of the course will be on interconnection network architectures used in multiprocessor and many-core systems, and designing for the communication requirements of various parallel architectures and cache coherence mechanisms.

In the first half of the course, lectures will cover the fundamentals of interconnection networks, getting to the research frontier at each leveltopology, routing, flow-control, microarchitecture, network interfaces, and system interactions. The second half of the course will focus on state-of-the-art research and case studies, using a mix of lectures, student presentations, paper readings, discussions, and debates on contrasting approaches. Towards the end, opportunities for interconnection networks in the presence of emerging trends such as heterogeneous systems and the Internet-of-Things will be explored.

A half-semester long research project will focus on solving open-ended research problems and can lead to publications in reputed journals/conferences/workshops. Projects aligned with students’ own graduate research (MS/PhD) will be encouraged if they have an interesting networks component.


Syllabus and Grading

ICN_outline.pdf

Simulation Infrastructure

gem5


FAQs

I am an undergrad. Would this course be useful for me?
If you are interested in applying to graduate school, and/or work in industry in the field of computer systems, expertise in this area will be a unique skill set to have. You will also get to work on open research problems in a relatively nascent field, in a structured setting (simulator, workloads etc that I will provide) without shooting in the dark.

I am a MS/PhD student and am (interested in) working in the area of Computer Architecture/Interconnection Networks/Networks-on-Chip. Can I take this course and use the course project towards my Masters/PhD thesis.
Yes. I am open to aligning the course project with your actual thesis work as long as there is an interesting networks component.

What is the required background? If I am an ECE student, do I need a CS (parallel programming/compilers/OS) background or if I am a CS student, do I need an ECE (circuits, RTL) background?
The required background is an understanding of computer architecture (ECE 4100 / ECE 6100 / CS 4290 / CS 6290) and familiarity with basic C++ programming. We will be using a simulator called gem5 which is written in C++. However, as with any research in computer architecture, you can choose to work on the circuits end of the computing stack, the microarchitecture end, or the software end. Interconnection Networks are no different. A diverse set of backgrounds is good, and in fact encouraged, as we read and discuss papers in the class. For the project, if someone wanted to implement a new NoC in Verilog instead of C++ and synthesize it to study power consumption, or wanted to hack LLVM to inject hints in the code that the NoC could use for power management, I would encourage both directions.

Is there scope for publications?
Yes, ample scope. Most of the projects will be on designing novel networks for emerging architectures. If the results from your course project look promising, we can write a paper on it over summer and I will fund your travel to go present it.


Textbook(s) and Readings

N. E. Jerger and L.-S Peh, “On-Chip Networks,” Morgan Claypool Publishers, 2009. [required]

W. J. Dally and B. Towles, “Principles and Practices of Interconnection Networks,” Morgan Kauffman Publishers, 2004. [optional] 

J. Duato, S. Yalamanchili, L. Ni, “Interconnection Networks: An Engineering Approach,” Morgan Kauffman Publishers, 2002. [optional]

There will be a lot of additional readings of recent research papers from conferences such as ISCA, MICRO, HPCA, ASPLOS, NOCS, DATE, DAC, ICCAD, ICCD, ISSCC


 Grading

  Lab 1     5%
  Lab 2   10%
  Lab 3   10%
  Paper Critiques   10% [Best of 10]
  Paper Presentation    10%
  Peer Reviews    10% [5% each]
  Proposal Presentation      5%
  Final Report   25%
  Project Presentation   15%

 


Schedule (Lectures)

  Week   Date Topic   Additional Readings Due Dates
1   Jan 11  (Mon)   L01: Introduction
  Jan 13  (Wed)   L02: Topology – I   Lab 1 (Jan 15 Fri @1pm)
2   Jan 18  (Mon)  Holiday
  Jan 20  (Wed)   L03: Topology – II
 3   Jan 25  (Mon)   L04: Routing
  Jan 27  (Wed)  L05: Deadlocks – I
 4   Feb 1 (Mon)  No Class  Lab 2 (Feb 02 Tue @11:55 pm)
  Feb 3 (Wed)  Lo6: Deadlocks – II
5   Feb 8 (Mon)  L07: Flow Control – I
 Feb 10 (Wed)   L08: Flow Control – II
 6  Feb 15 (Mon)   L09: Router Microarchitecture
 Feb 17 (Wed)   L10: SMART NoC
 6   Feb 22 (Mon)   No Class
  Feb 24 (Wed)   L11: System Interface
 6   Feb 29 (Mon)   TBD

Schedule (Presentations)

TBA


Honor Code:

Students are expected to abide by the Georgia Tech Academic Honor Code. Honest and ethical behavior is expected at all times. All incidents of suspected dishonesty will be reported to and handled by the office of student affairs. You will have to do all assignments individually unless explicitly told otherwise. You may discuss with classmates but you may not copy any solution (or any part of a solution).